With the miniaturization of the semiconductor integrated circuits, an integration degree of field effect transistors has risen at a pace of quadrupling in three years, thus allowing costs for photomask and design verification necessary for manufacturing integrated circuits to grow. As a result, a development cost of an application specific integrated circuit (ASIC) in which a user designs a fixed function in a custom-design manner in advance is rapidly increasing. In such a situation, a semiconductor device with which a designer can electrically program a desired circuit on a manufactured semiconductor chip, such as a field programmable gate array (FPGA), is drawing attention.
Incidentally, an FPGA has a problem that area efficiency is low and power consumption is large because the FPGA needs ten times or more of transistors compared with an ASIC in order to achieve the same function. In order to solve such a problem, research and development aiming to reduce an overhead of an FPGA and to reduce power consumption is being conducted. One of solutions to the above-described problem is to achieve a programmable wiring mounted with a variable resistance element (also called variable-resistance nonvolatile element) inside a multilayer wiring layer. The variable resistance elements include a resistance random access memory (ReRAM) using transition metal dioxide, a Nano Bridge (registered trademark) using an ion conductor, and the like.
PTL 1 discloses a variable resistance element using a solid ion conductor. The variable resistance element of PTL 1 includes an ion conductive layer, and a first electrode and a second electrode that are arranged adjacently to a counter surface of the ion conductive layer. The first electrode of the variable resistance element of PTL 1 is configured with a metal that can be ionized more easily than the second electrode, and the ion conductive layer is constituted of an electrolyte material including a metal ion of metal configuring the first electrode. In the variable resistance element of PTL 1, a resistance value of the ion conductor is adjusted by changing a polarity of applied voltage, thereby controlling a conductive state between the two electrodes.
An example in FIG. 14 is a crossbar circuit 100 in which a variable resistance element 110 of PTL 1 is arranged at an intersection point of buses in a crossbar. The crossbar circuit 100 of FIG. 14 includes a configuration in which variable resistance elements 110 are arranged at intersection points of a plurality of first wirings 121 to 126 and a plurality of second wirings 131 to 136. In FIG. 14, an element in an on-state is illustrated with a black square, and an element in an off-state is illustrated with a white square. The crossbar circuit 100 of FIG. 14 illustrates a wiring as a crossbar realized by putting variable resistance elements 110 on a diagonal line into the on-state.
PTL 2 discloses a crossbar switch using a variable resistance element as an ultra-large scale integration (ULSI). In the crossbar switch in PTL 2, it is disclosed that a variable resistance element is connected in series and used as a unit element.
An example in FIG. 17 is a crossbar circuit 200 in which a unit element 210 of PTL 2 is arranged at an intersection point of buses of a crossbar. The crossbar circuit 200 of FIG. 17 has a configuration in which unit elements 210 are arranged at intersection points of a plurality of first wirings 221 to 226 and a plurality of second wirings 231 to 236. In FIG. 17, an element in an on-state is illustrated with a black square, and an element in an off-state is illustrated with a white square. In the crossbar circuit 200 of FIG. 17, the unit element 210 is turned to the on-state by putting both of two variable resistance elements constituting the unit element 210 into the on-state, and the unit element 210 is turned to the off-state by putting both of the two variable resistance elements into the off-state. The crossbar circuit 200 of FIG. 17 illustrates a wiring as a crossbar realized by putting the unit elements 210 on a diagonal line into the on-state.
PTL 3 discloses a nonvolatile resistance network aggregate including two resistance networks in which a plurality of nonvolatile resistance elements are connected. The nonvolatile resistance network aggregate of PTL 3 performs writing in such a way that combined resistance values of the two resistor networks are different by using write means for writing into the two resistor networks.
PTL 4 discloses a content addressable memory cell using a variable-resistance nonvolatile storage element. The content addressable memory cell of PTL 4 includes a logical circuit that selects a current path in response to input data and a variable-resistance nonvolatile storage element that stores storage data, and includes a resistance network that changes a resistance value in response to a result of logical operation of input data and storage data. In addition, the content addressable memory cell of PTL 4 includes a charging/discharging circuit that changes delay time until outputting a signal input from a match line in response to the result of logical operation of input data and storage data.